The invention relates to an interrupt controller.
A device (a disk controller, for example) of a computer system might interact with a microprocessor of the system to perform a specific function (retrieval of data from a hard drive, for example). In this interaction, the device might need to temporarily interrupt ongoing operations of the microprocessor so that the microprocessor may service the device.
For example, the microprocessor might instruct a disk controller to retrieve a block of data from a hard disk drive, and while the disk controller is retrieving the data, the microprocessor might perform other operations, such as executing program code, for example. After the controller retrieves the data and stores the data in a system memory, the controller then might notify the microprocessor.
One way for the controller to notify the microprocessor is to generate an interrupt request. In response to the interrupt request, the microprocessor typically temporarily suspends any ongoing operations to, for example, read the data from the system memory and make decisions based on the data.
An interrupt request is typically communicated via an interrupt request signal. For an edge triggered interrupt request, the interrupt request signal changes logical states (changes from a high logical state to a low logical state, for example) to indicate the interrupt request. A level triggered interrupt request is typically indicated by the logical state (either high or low) of the interrupt request signal. Thus, an edge triggered interrupt request is indicated by a predetermined transition of the interrupt request signal, and a level triggered interrupt request is indicated by a predetermined logic level of the interrupt request signal.
A typical computer system has many devices that may need the attention of the microprocessor and thus, has many devices that may generate interrupt requests. However, the microprocessor may have only one interrupt request input pin and thus may only process one interrupt request at a time. To solve this dilemma, the computer system might have an interrupt controller to receive interrupt request signals from the devices, prioritize any interrupt requests that are indicated by these signals, and direct one interrupt request at time to the microprocessor for servicing.
One such interrupt controller may be the 8259A programmable interrupt controller made by Intel. The 8259A interrupt controller may receive up to eight different interrupt request signals on its eight interrupt input pins. Because many interrupt requests may occur during a short interval of time, the 8259A controller prioritizes the interrupt requests and (via an output interrupt request signal) furnishes indications of the requests one at a time to the interrupt request input pin of the microprocessor.
When the interrupt controller activates the interrupt request input pin of the microprocessor to indicate an interrupt request, an interrupt acknowledge sequence begins. During this sequence, the 8259A interrupt controller furnishes an interrupt value that is received by the microprocessor. For the microprocessor, the interrupt value identifies the interrupt signal that generated the interrupt request and serves as an index to a location in an interrupt vector table. This location stores the address of an interrupt handler routine which the microprocessor may execute to service the interrupt request. To process more than eight interrupt request signals, two or more of the 8259A interrupt controllers may be cascaded together in what is often called a master-slave arrangement.
The 8259A was primarily designed for use with only one microprocessor. Referring to FIG. 1, a multiprocessor computer system 8 might alternatively use an interrupt controller 10, such as an I/O Advanced Programmable Interrupt Controller (IOAPIC), Part No. 82093AA, that is made by Intel. The interrupt controller 10 communicates interrupt information with microprocessors 12 of the system 8 via an Advanced Programmable Interrupt Controller (APIC) bus 11.
The APIC bus 11 typically includes two bidirectional data lines and a clock line. When the interrupt controller 10 desires to communicate a given interrupt request to one or more of the microprocessors 12, the interrupt controller 10 furnishes signals to the APIC bus 11 that indicate such information as an APIC address (which identifies a particular microprocessor 12 to receive and service the interrupt request) and an index to an interrupt table.
The system 8 typically has additional circuitry to facilitate use of the interrupt controller 10. For example, to communicate with the APIC bus 11, each microprocessor 12 typically has a local APIC interface 14. The system 8 might also include a bridge circuit 16 that includes 8259A controllers to provide backward compatibility for older operating systems. This backward compatibility might be needed, for example, when the operating system first boots up the system 8, as described below.
As is typical, some older operating systems expect acknowledgment of interrupt requests over traditional system buses (and not over the APIC bus 11) during bootup of the system. For these older systems, the interrupt controller 10 may interact with the bridge 16 to emulate the response of the older 8259A controller(s) in what is referred to as a virtual wire mode. To accomplish this, during bootup, the interrupt controller 10 sends interrupt requests via messages over the APIC bus 11. However, acknowledgment of interrupt requests occur over the system buses.
Even when not operating in the virtual wire mode, the interrupt controller 10 may transmit interrupt requests to the microprocessor(s) in ways that do not include the APIC bus 11. For example, the interrupt controller 10 may furnish system management interrupt (SMI) requests and nonmaskable interrupt (NMI) requests directly to corresponding interrupt SMI and NMI input pins of the microprocessors 12.
The interrupt controller 10 may receive interrupt requests signals from many different sources, such as interrupt request lines of an Industry Standard Architecture (ISA) bus 18, a Peripheral Component Interconnect (PCI) bus (a bus conforming to PCI specification, version 2.0, available from PCI Special Interest Group, Portland, Oreg. 97214, for example (not shown) and/or a motherboard (not shown). All of these interrupt request signals are potential sources for interrupt requests, and each interrupt request signal may be associated with a different interrupt handler. Furthermore, with multiple microprocessors, handling of the different interrupt requests may be assigned to different ones of the microprocessors 12. To keep track of all of the information that is associated with the interrupt request signals, the interrupt controller 10 might include an interrupt request redirection table 20.
Typically, the redirection table 20 includes redirection table entries 21 (redirection table entries having sixty-four bit register locations called RTE[0], RTE[1], RTE[2] . . . RTE[22] and RTE[23], as examples), each of which is associated with a different interrupt request input pin of the interrupt controller 10. Referring to FIG. 2, each redirection table entry 21 may include, for example, a status bit field 28 that indicates a pending interrupt request for the associated input pin. Each redirection table entry 21 may also include a destination bit field 22 that stores a value which identifies the microprocessor(s) 12 to handle interrupt requests originating from the associated pin. An interrupt vector bit field 30 of the redirection table entry 21 may store a value that indicates an interrupt vector. Other bits of each redirection table entry 21, as examples, may specify how (level or edge triggered, as examples) interrupt requests are indicated at the associated input pin, and other bits of the redirection table entry 21 may be used to mask an interrupt request from propagating upstream from the interrupt controller 10 to one of the microprocessors 12.
The redirection table entries 21 are typically not used to store information for interrupt request signals that are generated internally by the interrupt controller 10. As a result, interrupts requests originating from these signals are not communicated to the microprocessors via the APIC bus 11. For example, logic inside the interrupt controller 10 may selectively logically combine signals that are received from some of the interrupt request input pins to generate an output SMI interrupt request signal (called SMIOUT#). Although the SMIOUT# signal appears on an SMI output pin 17 of the interrupt controller 10, an interrupt request indicated by the SMIOUT# signal may not be furnished to the APIC bus 11 because the SMIOUT# signal does not have an associated redirection table entry 21.
However, one way to allocate one of the table entries 21 to the SMIOUT# signal is to route the SMIOUT# signal from the output pin 17 to one of the input pins via an external network. By doing this, the SMIOUT# signal is assigned to the table entry 21 that is associated with the input that receives the SMIOUT# signal from the external network. However, an input pin is consumed for this purpose and external board routing may be required.
The interrupt controller 10 typically scans the table entries 21 one at a time in a round robin fashion to determine if the status bits 28 of an entry 21 indicates a pending interrupt request. As a result of the round robin scanning, the interrupt controller 10 may not immediately attend to a pending interrupt request. The interrupt controller 10 typically scans each entry 21, even if the interrupt request input pin that is associated with that entry is not being used.
Thus, there is a continuing need for an interrupt controller that reduces the latency of such a round robin polling mechanism. There is also a continuing need for an interrupt controller to store information in the redirection table for internally-generated interrupt request signals.